创锐讯通讯技术（上海）有限公司招聘信息！

发布时间：2007-03-16
工作地点：上海
信息来源：日月光华
职位类型：全职
职位描述
创锐讯通讯技术（上海）有限公司招聘信息！ 发信站: 日月光华 (2007年03月16日16:55:40 星期五) 创锐讯通讯 Atheros Communication 感兴趣的朋友可将简历发至 li.yang@ Position title and Job description Application Engineer Job Requirements : 1. BSEE required, MSEE preferred 2. 3+ years of experience of board level switch and LAN of ASIC design, preferably for PC and networking products 3. Must have good lab skills using various instruments such as spectrum analyzer, logic analyzer and scopes 4. Must be comfortable with both software & hardware 5. Specific knowledge of 802.3 6. Must be self motivated with good communication skills and an investig ative spirit. 7. Ability to be reactive to customer needs coupled with superior proble m solving and debug capabilities Job Responsibilities : 1. Assist RD to identify ASIC function 2. Solve customer’s issue 3. Design demoboard and EV board Team leader for Platform software Responsibilities: 1) To lead a team developing and maintaining platform software including: - Boot loaders - BSP/Drivers for switch chips - Base platform SDK 2) To perform Silicon testing for switch chips 3) To write technical documents for platform software 4) To provide technical support and training to FAE and customers Required Skills / Background: 1) BS/MS in CS/EE or equivalent; 2) At least 5 years embedded software development working experiences 3) Demonstrated working experience on embed CPU platform software such as B SP, Driver, boot loader etc. experience on LINUX/xBSD and MIPS is a plus. 4) Demonstrated working experience on writing makefiles and scripts (PERL, csh, sh). 5) Experience on switch/router development, well understanding customer req uirements. 6) 2-3 years of project/team lead experience 7) Eager to learn new technology and Self motivated, good team work player 8) Good command of English and Chinese both in speaking and writing. Team leader for AP software solutions Responsibilities: 1) To lead a team developing and maintaining AP software including: - Windows Vista Logo program including support for Vista Premium Logo - Router SDK - Configuration UI - Future applications like NAS, VoIP, Audio SDK etc 2) To write technical documents for platform software 3) To provide technical support and training to FAE and customers Required Skills / Background: 1) BS/MS in CS/EE or equivalent; 2) At least 5 years embedded software development working experiences 3) Demonstrated working experience on switch/router development, experience on router base on Linux/xBSD is a plus 4) Familiar with Vista logo for routers/gateway/WLAN APs is a plus 4) Experience on applications on routers such as configuration UI, VoIP, NA S, Audio etc is a plus 5) Well understanding customer requirements for switch/router. 6) 2-3 years of project/team lead experience 7) Eager to learn new technology and Self motivated, good team work player 8) Good command of English and Chinese both in speaking and writing. Digital Design Engineer --------------- Atheros Shanghai Job Overview: The Digital Design Engineer will be responsible for designing our wireless and SOC ASIC's. You will work closely with our architecture/algorithm engineers t o explore ideas for next generation products and then develop RTL to tern thes e ideas into customer solutions. Duties/Responsibilities: Chip features specification and RTL design Synthesis, verification, timing. FPGA emulation, lab validation and debugging. Qualifications: BS in Electrical/Electronics Engineering, MS preferred. 3 years experience with Verilog programming, logic synthesis and gate timing. A proven record of delivering successful ASIC's to the market is prefe rred. One or more advantages as following are highly desirable: A strong background in digital communication, signal processing and networking protocols; IC Design experiences in wireless communications and audio processing; Experie nces with ARM/DSP, AHB bus and External memory controller development. Good communication skills in English. Skills/Experience: Must be proficient in RTL coding, logic synthesis, gate-level simulations. Good knowledge of IC design backend flows. Experiences in IC life-cycle from conception, design, verification, top-level netlist with pads to tape-out, chip-testing and mass-production. FPGA, PCB or embedded SW skill is a plus. Digital Verification Engineer --------------- Atheros Shanghai Job Overview: The Digital Verification Engineer will be responsible for the simulation and v erification to craft our wireless and SoC ASICs. This position requires workin g with our architecture/algorithm and design engineers to prove correctness an d measure performance of our algorithms and RTL. Responsibilities include developing simulation environments used by our test d evelopment team to exercise Matlab and Verilog models, as well as evaluate thi rd party tools and develop methodologies which enhance our ability to produce high quality ASICs. Duties/Responsibilities: Developing simulation environments, and evaluate third party tools and develo p efficient methodologies. Design directed and random simulations to exercise Matlab and Verilog models. FPGA emulation, lab validation and debugging. Qualifications: BS in Electrical/Electronics Engineering, MS preferred. 3 years experience with various verification flows is required, with a proven track record of delivering successful ASICs. A strong background in software is a must, along with familiarity withASIC de sign flows. Good communication skills in English. Skills/Experience: Strong background and experience required in C/C++, Verilog, and ASIC verific ation techniques. Must be proficient in one or more major verification languages, such as Vera, Speceman, System C. Experience in the area of automatic code generation is a plus. Perl and Unix Shell experience is a plus. Good knowledge of IC design backend flows. FPGA, PCB or embedded SW skill is a plus. ATE Test Engineer--------------- Atheros Shanghai Job Overview: The ATE Test Engineer will develop ATE test software/hardware for Atheros IC p roducts. A strong understanding of the ATE test system structure, IC test pr ogram structure, DC/AC/RF test will be needed. An ideal candidate for this position is someone who enjoys the challenge of de veloping complicated IC test solutions, and is a fast learner with strong comm itment to results. Duties/Responsibilities: Design test hardware/software for Atheros SOC chips Debug bugs in the test programs Qualifications: BS Electrical or Computer Engineering, MS preferred 3 years of related ATE software development & debugging experience desired Good communication skills in English Experience on Teradyne Catalyst/iFLEX or Agilent 83K/93K preferred Skills/Experience: Good ATE systems knowledge Programming skills in C/VB languages Knowledge of Digital/Mixed-Signal/RF IC testing, Enjoys hands on lab work using test/measurement equipments (oscillosco pe, spectrum analyzer) Experience with Loadboard Design Strong trouble shooting and analytical skills Perl Script Language skill & Pattern Conversion skill a plus RF experience a plus Highly motivated, fast learner, team player with good communication sk ills Sr.IC Qualification Engineer Responsibilities for this position are: -chip qualification function in Shanghai; -designing the burn-in hardware; vector translation and bring up for IC burn-i n service; -owns the other reliability qualification such as ESD, HTOL, Latch-up….; -working with Atheros overseas experts and local reliability service vendors f or IC qualifications. Some restrictions for the candidates: Experience in Burn-in Board design, vector translation & bring up Trouble shooting capability in Hardware & vector Good comprehension in IC reliability qualification (Burn-in, ESD, HTOL, Latch- up…) Good relationship with burn-in service lab as a plus Good communication skills in English with overseas Thank you