意法半导体(上海)有限公司招聘

发布时间：2007-10-29
工作地点：上海
信息来源：交通大学就业网
职位类型：全职
职位描述
单位名称 意法半导体（上海）有限公司 所在地区 上海市

组织机构码 000000000 经济类型 【三资企业】外商独资 注册资金(万元) 0 货币类型 .

人事部门名称 人事部 通信地址 上海市遵义路100号虹桥上海城A座11层 邮编 200051

单位网站 招聘网址

独立法人 代理中介 已验证 已禁用 有协议 有招聘 注册用户

单位简介，包括单位规模、主营业务等

STMicroelectronics Ltd. is one of the world s leading independent semiconductor company with US$6.32 billion in global sales revenue for 2002. Asia Pacific accounts for 44% of our worldwide sales. With staff strength of over 40,000, STMicroelectronics offers a fully integrated range of services including manufacturing, designing, development, sales and marketing. In view of our business expansion, we invite high caliber talents to join our team in China

招聘信息及相关宣讲会

招聘公告主题 意法半导体(上海)有限公司招聘 招聘类别 全职

宣讲会地点 宣讲起始时间 宣讲结束时间

招聘内容 ANALOG IC DESIGN ENGINEERS (Shenzhen:10, Shanghai:5) - Master degree in Electronics Engineering, Microelectronics, IC design; - Good at English; - Self motivated and good attitude; - Proficient in major CAD tools and soft-wares. - Job description: Analyze and define the specs Do the technical feasibility Communicate with internal and external customer Use EDA tool to analyze and design the circuit to comply with the specs Test and debug the prototype on the bench DIGITAL IC DESIGN ENGINEERS (Shenzhen: 6, Shanghai: 5) - Master degree in Electronics Engineering, Telecom, Microelectronics, IC Design; - Good at English; - Self motivated and good attitude; - Proficient in major CAD tools and softwares. - Job description: Analyze and define a system using EDA tool Do the technical feasibility Communicate with internal and external customer Use EDA tool to analyze and design the circuit to comply with the specs Tasks: Front End (RTL, synthesis, DFT), Back End (P&R, STA, mask set), verification, silicon validation IC LAYOUT ENGINEERS (Shenzhen: 3) - Bachelor degree in Electronics Engineering, Microelectronics; - Good at English + Team work + knowledge sharing; - Self motivated and good attitude; - Familiar with major CAD tools and soft-wares. - Job description: Estimate the die size Do floor plan To convert the electrical schematics into physical layout using ST's processes Verification for DRC and LVS To prepare bonding diagram To extract parasitic devices for post-layout simulations Use EDA tool to implement the circuit layout 请有意向的同学将简历发至相应邮箱: 深圳公司:sz-post@ 上海公司:sh-post@

相关链接 ST公司介绍.doc